From NAND to Qubits.
Hardened, standards-compliant error-correction & encryption IP — FPGA & ASIC ready, built by the engineers who design storage silicon.
One vendor, the whole portfolio
Error correction, cryptography, signal processing, interface and processor — under one roof
11 cores · 5 families
- 156-bit BCH ECC
- QC-LDPC ECC
- qLDPC Decoder
Deterministic and soft-decision error correction for NAND, SSD and communications — plus syndrome decoding for quantum error correction.
Cryptography- AES-256 Encryption
- PBKDF2-HMAC Key-Derivation
Standards-compliant encryption and key derivation for data at rest and in flight.
Signal Processing- Stereo FM Tuner
- ADSP-2181 Compatible DSP
- DSP56001 Compatible DSP
- TMS320C54x Compatible DSP
Compatible cores that replace discontinued DSPs, plus a high-fidelity tuner — signal-processing assets that carry a platform through its life cycle.
Storage Interface- UFS Host Controller
An AXI4 host controller that connects an SoC straight to storage.
Processor- VR-RISC-V
A soft processor core that takes on the control, boot and management layer.
IP Catalog
Silicon-grade IP cores, ready to license
156-bit BCH ECC IP Core
Pick a correction strength and sector size — get drop-in Verilog RTL. Corrects up to 156 bit errors per sector, configurable from t=8.
QC-LDPC ECC IP Core (PAX_LDPC)
Inner LDPC + outer BCH + CRC32 targeting UBER < 1e-15. One rate-compatible architecture covers TLC and QLC by parameters only.
AES-256 Encryption IP Core
Standards-compliant AES-256 for data-at-rest (XTS) and data-in-flight (GCM). Roadmap — contact us for early access.
PBKDF2-HMAC Key-Derivation IP Core
RFC 8018 PBKDF2-HMAC in hardware. Midstate-cached SHA-256 core, AXI4-Lite, tunable work factor — pairs with AES-XTS for a full secure-storage datapath.
Stereo FM Tuner IP Core (DDC Receiver)
S/N 105 dB-class measured. NCO/mixer DDC → CIC/FIR decimation → CORDIC FM demod → 19 kHz pilot stereo decode → 24-bit I2S / S-PDIF / AES-EBU, with an adaptive multipath canceller.
ADSP-2181 Compatible DSP Core IP
Full 24-bit ADSP-21xx instruction encoding with cycle-accurate behaviour, SPORT / timer / autobuffer / BDMA / IDMA peripherals, verified across three simulators and synthesis.
DSP56001 Compatible DSP Core IP
24-bit datapath with 56-bit accumulators, X/Y/P triple bus and modulo/bit-reverse addressing. Instruction encoding cross-checked against official assembler listings at 98-99 %; core datapath runs real DSP kernels today.
TMS320C54x Compatible DSP Core IP
Modified Harvard architecture with one program bus and three data buses, a 6-stage pipeline, a 40-bit ALU with two 40-bit accumulators, and a 17x17 multiplier feeding a dedicated 40-bit adder for single-cycle MAC. Viterbi CSSU, exponent encoder and the C54x peripheral set are included.
UFS Host Controller IP Core (AXI4)
Drives a UFS device from your SoC: descriptor fetch and data DMA over AXI4, UFSHCI register model over APB3, and the full UTP/UniPro/data-link stack down to a SerDes-facing PHY adapter. 15 functional regressions pass on three simulators at 94 % statement coverage.
VR-RISC-V Core IP (RV32IMAC)
RV32IMAC + Zicsr in pure Verilog-2001. Five-stage in-order pipeline, 128 KB true dual-port TCM feeding instructions and data in one cycle each, one AXI4-Lite master for peripherals, and M / A / C extensions individually switchable at build time.
qLDPC Decoder IP Core
Bringing classical LDPC decoding expertise to quantum error correction — a real-time syndrome decoder for qLDPC codes. Early-access / research collaboration.
Storage Security Stack
A single datapath, key unwrap to NAND protection
PaxQubit ships every block of the secure-storage datapath — no multi-vendor integration.
PBKDF2
Unwraps the media key from a passphrase
AES-256-XTS
Encrypts data sector by sector
BCH / QC-LDPC
Corrects NAND bit errors
Why PaxQubit
From authentication to device lifetime
Brute-force-resistant keys
PBKDF2-HMAC key stretching (salt + tunable iterations) — ~0.1 s for the user, years for an attacker. RFC 8018 / NIST SP 800-132.
One-vendor secure storage
PBKDF2 → AES-XTS → BCH/LDPC, with the SHA core shared for eMMC RPMB — one vendor, less area and verification.
Longer NAND lifetime
Soft-decision QC-LDPC and high-strength BCH extend TLC/QLC NAND endurance and retention margins, keeping drives in service longer.
Silicon-grade & compliant
FPGA & ASIC-ready RTL aligned to FIPS, NIST, IEEE 1619, 3GPP and JEDEC.
Standards & compliance targets
Need a core for your controller or SoC?
Tell us your target device and correction/throughput goals. We respond within one business day.
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