UFS Host Controller IP Core (AXI4)

JEDEC UFSHCI 3.0 host controller in pure RTL — AXI4 master DMA, APB3 register file, UniPro link stack up to the M-PHY interface.

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15 / 15

Functional regressions, three simulators

94.35 %

RTL statement coverage (25 files)

Transfer request slots (8 task-management)

Overview

A UFS host controller sits between the SoC bus and the UFS storage device, turning driver-written descriptors into link transactions. This IP implements that whole path in pure RTL: an AXI4 master fetches transfer descriptors and moves payload data, an APB3 slave exposes the JEDEC UFSHCI 3.0 register model in a 4 KB window, and the transport, UniPro and data-link layers run down to a PHY adapter interface for an external SerDes.

Four asynchronous clock domains (APB, AXI/core, TX link, RX link) are crossed only through structural CDC — gray-coded asynchronous FIFOs, two-flop synchronizers and toggle handshakes — with matching FPGA and ASIC timing constraints supplied. Error handling is built in rather than bolted on: CRC corruption triggers NAC, NAC triggers frame replay from a dedicated buffer, and missing acknowledgements fall back to timer-driven retransmission, all reported through the standard error registers.

Verification is the differentiator. Fifteen functional regressions — link-up, end-to-end 4 KB/8 KB read/write, multi-frame UPIU reassembly, error injection and recovery, task management, multi-slot round-robin, abort drain, interrupt aggregation, segmented QUERY and a constrained-random stress suite with seed sweeps — all pass on three independent simulators, with 94.35 % RTL statement coverage measured over 25 files.

Parametric specification

Role	Host-side UFS controller between SoC bus and UFS device
Standards	JEDEC JESD223D (UFSHCI 3.0), JESD220E (UFS 3.1), MIPI UniPro v1.8 subset
Host bus	AXI4 master (descriptor fetch + data DMA) and APB3 slave (4 KB register window)
AXI configuration	Address 32-64 b, data 32/64/128 b, ID 1-8 b, burst up to 256 beats (parameterized)
Device interface	PHY adapter interface for an external M-PHY / SerDes (M-PHY outside IP scope)
Link	HS-Gear1 Rate B, 1 lane (≈1.46 Gbps), symbol clock ≈72.88 MHz
Slots	32 transfer requests + 8 task-management requests (parameterized)
Clock domains	4 asynchronous domains, structural CDC only (gray FIFO / 2FF / toggle handshake)
Error handling	CRC → NAC, frame replay buffer, timer-based retransmission, standard error reporting
8b/10b	Selectable — external SerDes performs coding, or use the built-in encoder/decoder
Verification	15 functional regressions on iverilog / ModelSim / XSim; 94.35 % statement coverage
Constraints	FPGA (Vivado XDC) and ASIC (SDC) timing constraints included
Implementation	Pure Verilog-2001 — no vendor primitives, no clock gating, no latches; inferred RAM
Status	RTL release candidate, regression-verified; crypto (UFSHCI CE) not supported

Performance

15 / 15

Functional regressions, three simulators

94.35 %

RTL statement coverage (25 files)

Transfer request slots (8 task-management)

Deliverables

Synthesizable Verilog-2001 RTL (25 files) with build-ordered file list
Regression testbench suite and UFS device bus-functional model
FPGA (XDC) and ASIC (SDC) timing constraint sets
Specification, architecture contract and integration notes (on request)

Supported Devices

FPGA — Xilinx (Vivado constraint set provided)ASIC — process-portable pure RTL with SDC

Targets / verified platforms. ASIC process numbers are characterized at integration.

Scope is stated explicitly rather than implied: this release targets the HS-Gear1, single-lane subset with TC0/CPort 0 only, and UFSHCI crypto (CE) is not implemented. The M-PHY itself is outside the IP — the controller presents a PHY adapter interface for your SerDes. Higher gears, additional lanes and crypto are scoped as engagement items.

Known design deviations from the standard (for example the register clear semantics that require a small driver adapter) are documented as a formal errata section in the specification, with verification evidence for each item — available on request at evaluation.

Documents

Full datasheet, integration guide and evaluation files are available on request. Request access below — we reply within one business day.

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Applications

SSD / storage SoC host controllers

Embedded systems adopting UFS in place of eMMC

Automotive and industrial storage subsystems

Test, validation and bring-up platforms for UFS devices

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