Signal Processing
DSP56001 Compatible DSP Core IP
A 24-bit fixed-point DSP core targeting Motorola DSP56001 compatibility — in active development, encoder verified against genuine assembler output.
Overview
The DSP56001 remains embedded in audio and industrial equipment long past its production life. This core targets that gap: a 24-bit fixed-point architecture with dual 56-bit accumulators, separate X, Y and program buses, and address generators with modulo and bit-reverse addressing.
Verification follows one principle — compare against genuine tool output, never against our own assumptions. Instruction encodings were cross-checked byte-by-byte against listings from the official Motorola assembler and a reference assembler across four independent corpora, reaching 97.6-99.2 % coverage with zero mismatches on two of them. The rebuilt datapath (decoder, ALU, address generators, sequencer) executes real DSP kernels — an FIR filter produces bit-correct results — with the full control-flow set (JMP, JSR/RTS, DO loops, conditional branches) working.
Parametric specification
| Role | Replacement core for obsolete DSP56001-based systems |
|---|---|
| Instruction set | Motorola DSP56000/56001, 24-bit encoding |
| Datapath | 24-bit fixed point, dual 56-bit accumulators (A/B), MAC |
| Buses | Separate X, Y data buses and program bus (16-bit addressing) |
| Address generation | R/N/M registers, post-increment, indexed, modulo and bit-reverse |
| Control flow | JMP / JSR / RTS (short and absolute), DO hardware loops, conditional branches |
| Encoding verification | Byte-level comparison against official assembler listings — 97.6-99.2 % across four corpora |
| Core execution | Real DSP kernels (e.g. FIR) execute bit-correctly in simulation |
| Timing model | Functional today; cycle-exact pipeline is a development item |
| Implementation | Pure Verilog RTL, vendor-primitive-free |
| Status | In active development — engagement-based scope |
Performance
Deliverables
- Synthesizable Verilog RTL core (decoder, ALU, address generators, sequencer)
- Instruction-encoding specification and encoder cross-check reports
- Self-checking test programs and simulation flow
- Joint-development scope proposal against your compatibility requirement (on request)
Supported Devices
Targets / verified platforms. ASIC process numbers are characterized at integration.
This core is offered as a development engagement rather than a finished drop-in product. Compatibility is verified at the instruction-encoding level and the datapath runs real kernels; the remaining scope is agreed against your requirement.
Verification figures are measured against published assembler listings; detailed reports, encoding specification and test material are available on request.
Documents
This core is on our roadmap. Contact us for early-access and roadmap details.
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