TMS320C54x Compatible DSP Core IP

A 16-bit fixed-point DSP core, instruction-level compatible with the TMS320C54x — designed as a drop-in library element for ASIC and FPGA.

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17x17

Parallel multiplier with a dedicated 40-bit adder — single-cycle MAC

3 + 1

Data memory buses plus one program bus (advanced multibus)

50 MIPS

20 ns single-cycle execution on the 0.35 um 3.3 V reference implementation

Overview

The TMS320C54x defined a generation of fixed-point signal processing, and a great deal of deployed telecom, voice and control equipment still runs code written for it. This core is instruction-level compatible with that architecture, so C54x assembly and the object code built from it carry over rather than being rewritten.

The datapath is built for signal processing rather than general control. An advanced multibus architecture gives the core one program memory bus and three separate 16-bit data memory buses, so a multiply-accumulate can read both operands and write a result without contention. A 40-bit ALU with a 40-bit barrel shifter and two independent 40-bit accumulators sits next to a 17x17 parallel multiplier coupled to a dedicated 40-bit adder, giving a non-pipelined single-cycle MAC. A compare-select-store unit accelerates the Viterbi add-compare-select operation, and an exponent encoder computes the exponent of a 40-bit accumulator in one cycle.

Addressing and peripherals follow the same reference architecture: two address generators with eight auxiliary registers and two auxiliary-register arithmetic units, circular-buffer and block-repeat support, 192K x 16 of addressable space split into 64K words each of program, data and I/O, and an on-chip peripheral set of PLL clock generator, TDM serial port, buffered serial port, 8-bit parallel host port interface, timer, interrupt controller and a software-programmable wait-state generator. The core is intended to be dropped into an ASIC as a library element or synthesised to FPGA.

Parametric specification

Role	Fixed-point DSP core for ASIC/FPGA integration and legacy C54x code reuse
Instruction set	TMS320C54x instruction-level compatible
Architecture	Advanced modified Harvard — 1 program bus + 3 x 16-bit data buses
Pipeline	6-stage: prefetch, fetch, decode, access, read, execute
ALU	40-bit ALU with 40-bit barrel shifter and two independent 40-bit accumulators; dual 16-bit mode
Multiplier	17 x 17 parallel multiplier + dedicated 40-bit adder, non-pipelined single-cycle MAC
DSP accelerators	Compare-select-store unit (Viterbi ACS), single-cycle exponent encoder
Addressing	2 address generators, 8 auxiliary registers, 2 ARAUs; circular buffer, block repeat, memory-mapped register and stack addressing
Address space	192K x 16 — 64K words program, 64K words data, 64K words I/O
Peripherals	PLL clock generator, TDM serial port, buffered serial port (BSP), 8-bit HPI, 16-bit timer, interrupt controller, software wait-state generator
Instruction features	32-bit long-word operands, two/three-operand reads, parallel load and store, conditional store, single-instruction and block repeat, fast return from interrupt
Reference implementation	0.35 um 3.3 V static CMOS, 20 ns single cycle (50 MIPS), 144-pin TQFP
Implementation	VHDL RTL with behavioural model set, testbench and an Altera synthesis set
Status	RTL available with an ASIC-level specification (pinout, memory map, register map, DC/AC characteristics)

Performance

17x17

Parallel multiplier with a dedicated 40-bit adder — single-cycle MAC

3 + 1

Data memory buses plus one program bus (advanced multibus)

50 MIPS

20 ns single-cycle execution on the 0.35 um 3.3 V reference implementation

Deliverables

Synthesizable VHDL RTL — core, peripherals and chip-level top
Behavioural model set for reference comparison, plus testbench and simulation scripts
Altera synthesis set and memory/IO cell wrappers
Specification with pinout, memory map, register map and DC/AC characteristics (on request)

Supported Devices

ASIC — 0.35 um static CMOS reference implementationIntel/Altera FPGA (synthesis set provided)

Targets / verified platforms. ASIC process numbers are characterized at integration.

Compatibility is stated at the instruction level: C54x assembly and the object code built from it are the compatibility target. The exact instruction and peripheral coverage against a specific C54x device variant is confirmed against your requirement during evaluation.

The 50 MIPS / 20 ns figure and the 144-pin TQFP package belong to the 0.35 um 3.3 V reference implementation described in the specification; on a modern process or an FPGA the operating frequency differs and is characterised for the target. Detailed specifications and test material are available on request.

Documents

Full datasheet, integration guide and evaluation files are available on request. Request access below — we reply within one business day.

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Applications

Life-extension of telecom, voice and control equipment built on the C54x

Viterbi-based channel decoding and communications signal processing

Voice and audio codecs, filtering and control loops

SoC integration — replacing an external DSP with an on-chip core

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