Error Correction
156-bit BCH ECC IP Core
Parametric BCH encoder/decoder for NAND flash & SSD controllers.
Overview
World-class performance — correcting up to t=156 bit errors on 1 K, 2 K and 4 K data words.
A clean-page (syndrome-zero) bypass skips the decoder back-end for error-free pages to save power and latency, and every frame reports an uncorrectable-error (UE) flag. The byte-serial datapath keeps the interface field-independent, so the same controller hooks up regardless of the chosen field GF(2^m).
Block Diagram
At a Glance
Parametric specification
| Role | NAND flash / SSD controller ECC engine |
|---|---|
| Code | Shortened BCH over GF(2^m), m = 13…24 |
| Correction strength t | Up to 156-bit; t = 8…156 |
| Sector / block size | 512 B … 1 MB |
| Datapath | 8-bit parallel, 1 byte/cycle streaming |
| Code rate | configurable by t (≈0.82–0.99) |
| Decoder pipeline | Syndrome → folded BM → Chien → gated XOR |
| Payload | data + meta (0…24 B in-band), auto cap-guard |
| Interfaces | REQ/DEN/RDY/EN handshake · APB status (UE flag) |
| Power features | clean-page bypass, per-frame UE reporting |
| Verification | ModelSim full-chain vs cycle-accurate Python reference + exhaustive matrix equivalence proof |
| Status | RTL-complete, simulation-verified — FPGA/ASIC characterization in progress |
Correction-strength selection guide
| SKU | Correction t (bits / 1 KB sector) | Parity (1 KB) | Typical use |
|---|---|---|---|
| BCH-t8 | 8 | 14 B | Light ECC for SLC NAND / low-BER media |
| BCH-t16 | 16 | 28 B | Mainstream SLC / MLC NAND |
| BCH-t32 | 32 | 56 B | MLC / early TLC NAND |
| BCH-t48 | 48 | 84 B | TLC NAND controllers |
| BCH-t64 | 64 | 112 B | High-endurance TLC |
| BCH-t96 | 96 | 168 B | High-density TLC / QLC |
| BCH-t120 | 120 | 210 B | QLC / high-retention storage |
| BCH-t128 | 128 | 224 B | High-strength QLC / enterprise endurance |
| BCH-t156 Baseline | 156 | 273 B | Maximum strength — extreme-BER media, high-reliability memory (reference baseline) |
Deliverables
- Synthesizable Verilog RTL (encoder, decoder, GF multipliers, correction logic, PAX wrappers)
- Cycle-accurate Python reference model and equivalence verifier
- ModelSim full-chain testbench (clean / correct / UE / pad vectors)
- Datasheet, manual and integration guide (on request)
Supported Devices
Targets / verified platforms. ASIC process numbers are characterized at integration.
Differentiator: t (8…156) and sector (512 B…1 MB) provided as drop-in RTL, with patent-based area optimizations.
Shares its 3-layer interface with the PAX_LDPC core, so controllers can upgrade BCH → LDPC with minimal integration change.
Documents
Full datasheet, integration guide and evaluation files are available on request. Request access below — we reply within one business day.
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