Processor
VR-RISC-V Core IP (RV32IMAC)
A 32-bit RISC-V soft processor with valid-ready handshaking at every pipeline boundary and 128 KB of tightly-coupled memory.
Overview
A 32-bit RISC-V soft processor built for FPGA, implementing RV32IMAC + Zicsr in Machine mode. What distinguishes it structurally is that every stage boundary of the five-stage in-order pipeline carries a valid-ready handshake: data advances on valid, and when a downstream stage lowers ready the back-pressure propagates upstream in the same cycle. Stalls therefore fall out of the interconnect rather than out of a separate stall FSM, and each module can be verified on its own against the same handshake contract.
Memory is a 128 KB true dual-port TCM: port A serves instruction fetch read-only in one cycle, port B serves loads and stores with byte enables. Because the two never contend, the instruction-bus arbiter of a conventional five-stage core disappears and fetch latency is fixed at one cycle. Everything above 0x4000_0000 is routed by an address decoder to an AXI4-Lite master, which issues the AW and W channels in parallel so a serialising slave cannot deadlock it. Unmapped space returns DECERR and traps precisely.
Verification is where the core earns its status. The same test source builds three ISA configurations (RV32IMAC, RV32IMC, RV32I) and all pass, the MDU and the compressed-instruction expander are verified standalone, and eight deliberate RTL mutations were all caught by the regression suite. Directed tests cover the interactions between extensions and the TCM boundary conditions, and the valid-ready protocol is checked by assertions across the whole pipeline with no violations.
Block Diagram
Parametric specification
| Role | Embedded control-plane / management processor for FPGA SoC |
|---|---|
| ISA | RV32IMAC + Zicsr, Machine mode |
| Pipeline | 5-stage in-order (IF/ID/EX/MEM/WB), single issue, valid-ready at every boundary |
| Forwarding | EX/MEM, MEM/WB and WB bypass → EX; load & AMO completion forwarding; load-use costs 1 cycle |
| Branches | Static not-taken, resolved in EX, 2-cycle mispredict penalty |
| M extension | 32-cycle iterative multiply/divide unit, no DSP blocks, valid-ready to EX |
| A extension | LR/SC + 9 AMO operations, MEM 2-pass read-modify-write, single-hart atomicity |
| C extension | 16-bit compressed instructions, IF halfword alignment buffer with word-boundary straddle handling |
| Memory | 128 KB true dual-port TCM (32 K × 32-bit) — port A fetch read-only, port B load/store with byte enables |
| Memory map | 0x0000_0000–0x0001_FFFF TCM · 0x4000_0000+ external AXI · unmapped returns DECERR |
| External bus | AXI4-Lite master ×1, AW/W issued in parallel, outstanding depth 1 |
| Exceptions | Precise, committed in MEM — access fault, illegal, breakpoint, misaligned, ECALL |
| Interrupts | Machine-mode MEI / MTI / MSI, 2-FF synchronised, priority MEI > MSI > MTI |
| Interrupt latency (measured) | 6 cycles worst-case on single-cycle streams; 40 cycles worst-case during divide. T_irq(worst) = 6 + max(T_mdu, T_dbus), T_mdu = 34 |
| Configuration options | M / A / C extensions can each be disabled to reduce area; reset vector, TCM size and memory init file are set at build time |
| Clock / reset | Single clock domain; asynchronous assert, synchronous de-assert, active low |
| Implementation | Pure Verilog-2001 RTL — no function / task / generate constructs, no vendor primitives |
| Verification | Three ISA builds + 10 random seeds pass; MDU and RVC expander verified standalone; 8/8 mutation detection; 10 directed extension-interaction tests; 0 valid-ready protocol assertion violations |
| Status | RTL complete, simulation-verified — FPGA characterization at target-board selection |
Performance
Variants
RV32IMAC
Full configuration — integer, multiply/divide, atomics and compressed instructions.
RV32IMC
EN_A_EXT = 0 — drops the atomic unit and its 2-pass memory path where single-threaded firmware does not need it.
RV32I
EN_M/A/C_EXT = 0 — smallest build; the removed instructions raise an illegal-instruction trap.
Deliverables
- Synthesizable Verilog-2001 RTL — core, MDU, compressed-instruction expander, dual-port TCM, DBus decoder, AXI4-Lite bridge, top-level integration
- Testbench with an AXI4-Lite slave BFM (randomised ready toggling and response delay) and a self-checking test program covering all three ISA builds
- Directed testbenches for extension interaction and TCM boundary conditions
- iverilog build/simulation script and ModelSim/Questa run script
- Data sheet, RTL implementation manual and integration guide (on request)
Supported Devices
Targets / verified platforms. ASIC process numbers are characterized at integration.
Scope is stated rather than implied. Atomicity is guaranteed within a single hart — AXI4-Lite has no exclusive access, so atomicity across external multi-master systems is not claimed. Interrupt acceptance is deferred while a multi-cycle instruction is in flight; the delay is finite, deterministic and measured (see the interrupt-latency row), and exception precision is preserved in every case. A cross-port read-during-write on the TCM is device-dependent, so code download must be separated in time from fetch.
Resource usage and Fmax are not quoted here: they depend on synthesis options and constraints, and are supplied as a separate synthesis report once the target device is fixed. The data sheet, register-level detail and the full verification material are available on request at evaluation.
Documents
Full datasheet, integration guide and evaluation files are available on request. Request access below — we reply within one business day.
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