IP Catalog
IP Core Catalog
Error correction, cryptography, signal processing, storage interface and processor IP for NAND/SSD controllers, communications, secure systems and long-life embedded platforms. Headline specs below; full datasheets on request.
Error Correction IP
156-bit BCH ECC IP Core
Pick a correction strength and sector size — get drop-in Verilog RTL. Corrects up to 156 bit errors per sector, configurable from t=8.
QC-LDPC ECC IP Core (PAX_LDPC)
Inner LDPC + outer BCH + CRC32 targeting UBER < 1e-15. One rate-compatible architecture covers TLC and QLC by parameters only.
qLDPC Decoder IP Core
Bringing classical LDPC decoding expertise to quantum error correction — a real-time syndrome decoder for qLDPC codes. Early-access / research collaboration.
Security & Crypto IP
AES-256 Encryption IP Core
Standards-compliant AES-256 for data-at-rest (XTS) and data-in-flight (GCM). Roadmap — contact us for early access.
PBKDF2-HMAC Key-Derivation IP Core
RFC 8018 PBKDF2-HMAC in hardware. Midstate-cached SHA-256 core, AXI4-Lite, tunable work factor — pairs with AES-XTS for a full secure-storage datapath.
Signal Processing & Compute IP
Stereo FM Tuner IP Core (DDC Receiver)
S/N 105 dB-class measured. NCO/mixer DDC → CIC/FIR decimation → CORDIC FM demod → 19 kHz pilot stereo decode → 24-bit I2S / S-PDIF / AES-EBU, with an adaptive multipath canceller.
ADSP-2181 Compatible DSP Core IP
Full 24-bit ADSP-21xx instruction encoding with cycle-accurate behaviour, SPORT / timer / autobuffer / BDMA / IDMA peripherals, verified across three simulators and synthesis.
DSP56001 Compatible DSP Core IP
24-bit datapath with 56-bit accumulators, X/Y/P triple bus and modulo/bit-reverse addressing. Instruction encoding cross-checked against official assembler listings at 98-99 %; core datapath runs real DSP kernels today.
TMS320C54x Compatible DSP Core IP
Modified Harvard architecture with one program bus and three data buses, a 6-stage pipeline, a 40-bit ALU with two 40-bit accumulators, and a 17x17 multiplier feeding a dedicated 40-bit adder for single-cycle MAC. Viterbi CSSU, exponent encoder and the C54x peripheral set are included.
Storage Interface IP
Processor & SoC IP
Parametric comparison
IP Core Catalog
| IP Core | Standard / Role | Key configuration | Target | Status | |
|---|---|---|---|---|---|
| 156-bit BCH ECC IP Core Best-seller | NAND/SSD ECC · shortened BCH codec | t=8…156 (max 156-bit), sector 512 B…1 MB | FPGA / ASIC | RTL-complete | Request Quote |
| QC-LDPC ECC IP Core (PAX_LDPC) Featured | 3D NAND TLC/QLC SSD ECC · concatenated QC-LDPC | rate 0.897 (TLC) / 0.844 / 0.802 (QLC), Z=256 | FPGA (verified) / ASIC | FPGA-verified | Request Quote |
| AES-256 Encryption IP Core Coming soon | FIPS-197 · SP 800-38A/D/E · IEEE 1619 | 256-bit key, XTS / GCM / CBC / CTR modes | FPGA / ASIC | Roadmap | Request Quote |
| PBKDF2-HMAC Key-Derivation IP Core Featured | RFC 8018 / RFC 2104 · FIPS 180-4 · NIST SP 800-132 | PBKDF2-HMAC-SHA-256/512, tunable iteration count, AXI4-Lite | FPGA / ASIC | RTL-complete | Request Quote |
| Stereo FM Tuner IP Core (DDC Receiver) NewFeatured | FM broadcast (pilot-tone stereo) · AES3 / S-PDIF audio output | Direct RF sampling DDC, CORDIC demod, multipath canceller, 24-bit audio | FPGA / ASIC | FPGA-verified | Request Quote |
| ADSP-2181 Compatible DSP Core IP New | ADSP-21xx instruction set (24-bit encoding) | Core + SPORT / timer / autobuffer / BDMA / IDMA, cycle-accurate | FPGA / ASIC | RTL-complete | Request Quote |
| DSP56001 Compatible DSP Core IP Research | Motorola DSP56000/56001 instruction set (24-bit) | 24-bit datapath, 56-bit accumulators, X/Y/P buses — development stage | FPGA / ASIC | Roadmap | Request Quote |
| TMS320C54x Compatible DSP Core IP New | TI TMS320C54x instruction set (16-bit fixed point) | 1 program + 3 data buses, 6-stage pipeline, 40-bit ALU / dual 40-bit ACC, TDM & buffered serial ports, HPI | ASIC / FPGA | RTL-complete | Request Quote |
| UFS Host Controller IP Core (AXI4) NewFeatured | JEDEC JESD223D (UFSHCI 3.0) · JESD220E (UFS 3.1) · MIPI UniPro v1.8 subset | AXI4 master DMA + APB3 registers, 32 transfer slots, HS-Gear1 1-lane | FPGA / ASIC | RTL-complete | Request Quote |
| VR-RISC-V Core IP (RV32IMAC) NewFeatured | RISC-V RV32IMAC + Zicsr (Machine mode) | 5-stage pipeline, 128 KB dual-port TCM, AXI4-Lite master, per-extension M/A/C toggles | FPGA / ASIC | RTL-complete | Request Quote |
| qLDPC Decoder IP Core NewResearch | Quantum error correction · qLDPC syndrome decode | BP / BP+OSD, bivariate-bicycle codes | FPGA / research | Roadmap | Request Quote |
Full datasheet, integration guide and evaluation files are available on request. Request access below — we reply within one business day.